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? semiconductor MSM7661 1/40 ? semiconductor MSM7661 ntsc/pal digital video decoder general description the MSM7661 is an lsi device which converts digitally sampled ntsc or pal video signals to 8-bit digital data based on itu-rbt601. the input video signals available are composite video signals and s video signals. the composite video signals are converted to yuv data via a 2-dimensional y/c separation circuit. the a-to-d converted data is data sampled at pixel clock frequency or double pixel clock frequency (the built-in decimation filter is used). input signal synchronization can lock synchronization and color burst at high speed through internal digital processing. features (? indicates a new feature compared with msm7660) ? input video signals include the following two types of digital data that are a-to-d converted at pixel frequency or double pixel frequency : ntsc/pal composite video signal ntsc/pal s video signal 8-bit y/8-bit c (cbcr) output (conforms to itu-rbt601) ycbcr 4 : 2 : 2 ycbc 4 : 1 : 1 ? 2-dimensional y/c separation using adaptive comb filter (this filter is bypassed for s video signal input) ntsc: 3 lines/2 lines pal: 2 lines (3 virtual lines) ? input signal synchronization can lock synchronization and color burst at high speed through internal digital processing. sampling frequency 13.5 mhz (itu-r601) 12.27 mhz (ntsc square pixel) 14.31818 mhz (ntsc 4fsc) 14.75 mhz (pal square pixel) ? internal agc/acc circuit switchable between agc and mgc (fixed gain) ? built-in decimation filter located in the input stage allows easy configuration of an external filter circuit (located ahead of a/d converter). ? automatic ntsc/pal recognition (only for itu-rbt.601) ? sleep mode ? multiplex signal recognition (teletext) data during vertical blanking is output in 8 bits in through mode. i 2 c-bus interface ? 3.3 v single power supply (each i/o pin is 5 v tolerable) ? package: 64-pin plastic qfp (qfp64-p-1414-0.80-bk) (product name: MSM7661gs-bk) preliminary e2f0008-18-31 this version: mar. 1998
? semiconductor MSM7661 2/40 block diagram scl synchronization block luminance block (agc + lpf) prologue block lum. chr. decimation filter line memory (1kbyte) 2 (2dim. y/c separate) chrominance block (acc + lpf) i 2 c-bus control logic test control logic epilogue block (output formatter) sda reset_l te test1 test2 (sleep) odd clkx2 pllsel vvalid hvalid vsync_l hsync_l hsy clkx2o syssel clksel clkxo mode[3:0] yd[7:0] vco_cp cd[7:0] y[7:0] c[7:0] sync (csync_l) decimation filter
? semiconductor MSM7661 3/40 pin configuration (top view) cd[0] cd[1] cd[2] cd[3] cd[4] cd[5] cd[6] cd[7] cvbs[0] cvbs[1] cvbs[2] cvbs[3] cvbs[4] cvbs[5] cvbs[6] cvbs[7] v dd gnd scl sda mode[0] mode[1] mode[2] mode[3] reset_l pllsel clksel test1 sleep te gnd v dd v dd gnd clkx2 hsy sync vco_cp clkx2o syssel clkxo hsync_l vsync_l hvalid vvalid odd gnd v dd c[0] c[1] c[2] c[3] c[4] c[5] c[6] c[7] y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 49 63 62 61 60 59 58 57 56 55 54 53 52 51 50 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 32 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64-pin plastic qfp
? semiconductor MSM7661 4/40 pin descriptions pin 1 to 8 9 to 16 17 18 19 20 21 to 24 26 27 28 29 type i i i i/o i i i i i symbol cd[0 to 7] cvbs[0 to 7] v dd gnd scl sda mode[0 to 3] pllsel 25 i reset_l clksel test1 sleep description chrominance signal input pin (valid only for s video input) composite signal input pin luminance signal is input for s video input. i 2 c-bus clock pin i 2 c-bus data pin mode input pins. these pins are internally pulled-down. unused. fixed to "h" externally. clock select input pin. "l" ? double-speed 27 mhz, "h" ? ordinary 13.5 mhz input pin for testing. normally "l". internally pulled down. sleep mode setting pin. normally "l". internally pulled down. mode[3] 0: composite 1: s video mode[1:0] 00: itu-r601 01: square pixel 10: 4fsc (only for ntsc) 11: none if itu-r signals are input when registers are set to automatic ntsc/pal recognition mode, ntsc/pal is automatically recognized irrespective of mode2 setting. set each pin to "l" level at composite signal input. mode[2] 0: ntsc 1: pal 30 i te input pin for testing. normally "l". internally pulled down. 31 gnd system reset pin (active at "l") 32 v dd
? semiconductor MSM7661 5/40 description chrominance signal output pins luminance signal output pins field display output pin outputs "h" for odd field. vertical valid line timing output pin horizontal valid pixel timing output pin v sync output pin h sync output pin internal operation clock output pin clock output pin symbol y[7 to 0] c[7 to 0] v dd gnd odd vvalid hvalid vsync_l hsync_l clkxo syssel clkx2o vco_cp type o o o o o o o o o o o pin 33 to 40 41 to 48 49 50 51 52 53 54 55 56 57 58 59 display select output pin for ntsc-pal detect / multiplex signal detect / hlock sync detect. selection by register. (default : ntsc-pal detect) ntsc mode : "l", pal mode : "h" multiplex signal detect : "h" hlock sync detect : "h" sync i/o 60 clamp signal timing output pin for a/d converter hsy o 61 clock input pin clkx2 i 62 gnd 63 v dd 64 unused. open normally. composite sync output. unused as input pin.
? semiconductor MSM7661 6/40 absolute maximum ratings parameter power supply voltage input voltage power consumption storage temperature symbol v dd v i p w t stg condition rating C0.3 to +4.5 C0.3 to +5.5 800 C55 to +150 unit v v mw c recommended operating conditions parameter power supply voltage power supply voltage "h" level input voltage "l" level input voltage symbol v dd gnd v ih v il condition typ. 3.3 0 unit v v v v operating temperature ta 25 c min. 3.0 2.2 0 0 max. 3.6 v dd 0.8 70
? semiconductor MSM7661 7/40 electrical characteristics dc characteristics *1: hsync_l, vsync_l, syssel *2: y[7:0], c[7:0], hsy, hvalid, vvalid, odd, clkxo *3: clkx2o *4: mode[3:0], sleep, test1, te parameter symbol v oh condition i oh = C6 ma (*2) i oh = C8 ma (*3) i ol = 6 ma (*2) typ. unit "l" level output voltage v ol i ol = 8 ma (*3) v min. 0.7 v dd max. 0.4 "h" level output voltage v input leak current i i v i = gnd to v dd m a C10 +10 output leak current i o v i = gnd to v dd m a C10 +10 power supply current (operating) clk = 27 mhz 140 ma 180 sda output voltage sdav l v 0 0.4 sda output current sdai o ma 3 i oh = C4 ma (*1) i ol = 4 ma (*1) r pull-down = 20 250 50 k w (*4) i ddo clk = 13.5 mhz power supply current (operating) v dd = 3.3 v 110 ma 150 i ddo2 power supply current (sleep) i dds sleep on 1 ma 5 (ta = 0 to 70c, v dd = 3.3 v 0.3 v) v dd = 3.3 v
? semiconductor MSM7661 8/40 ac characteristics (single speed mode) ac characteristics (double speed mode) parameter symbol condition min. typ. max. unit clkx2 cycle time t clkx1 itu-r601 74.07 ns ntsc 4fsc 69.84 ns ntsc square pixel 81.5 ns pal square pixel 67.8 ns input data setup time t is1 clksel : h 0 ns input data hold time t ih1 clksel : h 30 ns output data delay time 1 (*) t odx1 clksel : h 9 32 ns output data delay time 2 (*) t od1 clksel : h 3 13 ns t cxd1 clksel : h 6 19 ns output clock delay time (*) (internal) t cd1 clksel : h 6 19 ns ( *out p ut load 15 p f ) scl clock cycle time t c_scl rpull_up = 4.7 k w 200 ns low level cycle t l_scl rpull_up = 4.7 k w 100 ns output clock delay time (*) (external) (ta = 0 to 70c, v dd = 3.3 v 0.3 v) clkx2 duty t d_d1 4060% parameter symbol condition min. typ. max. unit clkx2 cycle time t clkx2 itu-r601 37.05 ns ntsc 4fsc 34.9 ns ntsc square pixel 40.75 ns pal square pixel 33.9 ns input data setup time t is2 clksel : l 5 ns input data hold time t ih2 clksel : l 15 ns output data delay time 1 (*) t odx2 clksel : l 9 32 ns output data delay time 2 (*) t od2 clksel : l 3 13 ns t cxd2 clksel : l 6 19 ns output clock delay time (*) (internal) t cd2 clksel : l 6 19 ns ( *out p ut load 15 p f ) scl clock cycle time t c_scl rpull_up = 4.7 k w 200 ns low level cycle t l_scl rpull_up = 4.7 k w 100 ns output clock delay time (*) (external) (ta = 0 to 70c, v dd = 3.3 v 0.3 v) clkx2 duty t d_d2 4060%
? semiconductor MSM7661 9/40 input and output timing clkx2o clkx2 clkxo cvbs cd t cxd1 clksel:h t cd1 t is2 t ih2 t cxd2 t cd2 not valid not valid not valid not valid t clkx1 clksel:l t od1 t odx1 hsy, hvalid, vvalid, odd, syssel, y,c, hsync_l, vsync _ l t clkx2 t odx2 t is1 t ih1 reset_l * t od2 12 789 ack 12 3-8 9 ack s start condition p stop condition data line stable: data valid change of data allowed scl sda msb t c_scl i 2 c-bus interface input/output timing the basic input/output timing of the i 2 c-bus interface is as follows. i 2 c-bus basic input/output timing * when changing the state of reset_l input in double speed mode, avoid doing it in the period of setup time and hold time (the shaded portion).
? semiconductor MSM7661 10/40 block description 1. prologue block the prologue block performs y/c separation by inputting data. data can be input either at ordinary pixel frequency (itu-r : 13.5 mhz) or at double pixel frequency (itu-r: 27 mhz). when the double pixel frequency is used, data is processed after changing to the ordinary pixel frequency via a decimeter circuit. by changing the register setting, the decimeter circuit can be bypassed irrespective of whether data is input at ordinary pixel frequency or at double pixel frequency. the prologue block performs y/c separation using a 2-dimensional adaptive comb filter when composite signals (cvbs) are input. the following operation modes can be changed via the i 2 c-bus. the * mark indicates a default. the default is a state that is selected when reset. 1) video input mode select composite video input * s video input 2) video input mode select auto ntsc/pal select* (only for itu-r601) dependent on operation mode selected when itu-r601 is selected, the video input mode is automatically determined by the number of lines per field. 3) operation mode select ntsc ccir601 13.5 mhz* mtsc square pixel 12.27 mhz ntsc 4fsc 14.31818 mhz pal ccir601 13.5 mhz pal square pixel 14.75 mhz 4) decimeter circuit pass/bypass select decimeter circuit is passed. * decimeter circuit is bypassed. 5) y/c separation mode select adaptive comb filter is used. * unadaptive comb filter is used. trap filter is used. the adaptive comb filter detects the correlation up to 3 lines between continuous lines. the y/ c is separated by the comb filter according to the way of correlation if theses lines are correlated. the y/c is separated by the trap filter if these lines are not correlated (only 2 lines in the case of pal). in the unadaptive comb filter, the y/c is always separated by removing the luminance component based on the average of preceding and following lines (when there is the correlation between 3 lines).
? semiconductor MSM7661 11/40 if the comb filter is not used, the y/c is separated by the trap filter. the y/c separation circuit is bypassed by s video signal input. in adittion, the functions of this block work only when lines are valid as image information. the processing of cvbs signals is not made during v-blanking. 2. luminance block the luminance block removes synchronous signals from the signals containing luminance components after y/c separation. the signals are corrected and output as luminance signals. the luminance signal output level gain control functions include three selectable modes such as agc (auto gain control), mgc (manual gain control) + no clamp, and mgc + pedestal clamp. in the agc mode, the luminance level amplification is determined by comparing the depth of sync with the reference value. the default is 40ire which can be changed by the register. the input is a sync chip clamp type. in the mgc + no clamp mode, the luminance signal output level is not affected by the input, and the amplification and black level are controlled by setting the register. in the mgc + pedestal clamp mode, the signal output level is clamped to the pedestal level of the input. the signal amplification and black level are controllable from the clamped point by setting the register. this block can select the follwing operation modes. 1) use of prefilter and sharp filter used* not used these filters are used for enhancing the edges of luminance component signals. 2) selection of aperture bandpass filter coefficient middle range* high range 3) coring range select off* 4lbs 5lbs 7lbs 4) aperture weighting factor select 0* 0.25 0.75 1.5 the profile of these signals can be corrected by coring and aperture correction. 5) use of pixel position correction circuit used* not used 6) agc loop filter time constant select slow factor value 1/1024n
? semiconductor MSM7661 12/40 medium 1/64n* fast 1/n fixed 0 7) parameter for agc reference level fine adjustment 8) parameter for sync separation level fine adjustment the black level is controlled. when the default is specified, the depestal position is output as a black level (=16). 9) pedestral clamp selecton pedestral clamp is not used.* pedestral clamp is used. (agc will not operate) 3. chrominance block this is a chroma signal processing block. the following modes can be selected. 1) use of color bandpass filter used* not used 2) acc loop filter time constant select slow factor value 1/1024n medium 1/64n* fast 1/n fixed 0 3) acc reference level fine adjustment 4) parameter for burst level fine adjustment the threshold level for valid chroma amplitude is selected based on a color burst ratio. 0.5 0.25* 0.125 off 5) color killer mode select auto color killer mode* forcible color killer 6) parameter for color subcarrier phase fine adjustment in this block, chroma signals pass through the chroma bandpass filter to cut an unnecessary band. to maintain a constant chroma level, uv demodulation is performed on these signals via the acc correction circuit. (this filter can be bypassed.) if the demodulation result does not reach a specified level, color killer signals are generated to fix the acc gain. this functions as an auto color killer control circuit. the uv demodulation result is output as chrominance signals via a low pass filter.
? semiconductor MSM7661 13/40 4. synchronization block this is a synchronizing signal processing block. chip output synchronizing signals and synchronizing signals for internal use are generated by this block. various signals are output in this block and the following operation modes can be selected. 1) sync threshold level adjustment 2-1) fine adjustment of hsy signal (start side) 2-2) fine adjustment of hsy signal (stop side) 3) hsy signal enable select high level active* these signal are used to sync chip and clamp timing to the a/d converter 4) fine adjustment of hsync_l signal 5-1) fine adjustment of hvalid signal (start side) 5-2) fine adjustment of hvalid signal (stop side) 6-1) fine adjustment of vvalid signal (start side) 6-2) fine adjustment of vvalid signal (stop side) the data signals are transmitted or received at the rising edge of the hvalid signal. 7) tv, vtr mode select tv mode vtr mode* the tv mode outputs a fixed pixel number per one line and absorbs a jitter that does not appear on the tv receiver normally. the vtr mode outputs the results of decoding in accordance with the hsync signal regardless of whether a jitter exists or not.
? semiconductor MSM7661 14/40 5. epilogue block the epilogue block outputs uv signals from the chrominance block and y signals from the luminance block in the format based on the signal obtained by setting of the control register. in this block, the following modes can be selected. 1) display of blue back when synchronization fails. off on* 2) output signal y/cbcr format select ycbcr 4 : 2 : 2* ycbcr 4 : 1 : 1 the chrominance signal (u, v component) outputs cb and cr data to the c pin in an output format described later. 3) selection of 8-bit chroma signal output format offset binary* 2's complement 4) output pin enable select high impedance output enable* 5) multiplex signal detect level adjustment the levels are configured to be variable when detecting data, such as multiplex signal, which is present for the vertical blanking interval. if defining 60 as the black level and 200 as the white level, the levels between them are valued as 100 ire, the data detect levels are set to 8 steps on a 57 ire basis. 6) various modes detection ntsc/pal detect mode* multiplex signal detect mode hsync synchronization detect mode 7) output signal phase control 6. i 2 c control block this is the serial interface block based on the i 2 c standard of phillips corporation. this block functions only as a slave-receiver. the external control can set the internal registers (mra, mrb, hsyt, etc.). 7. test control block this block is used to test this lsi. normally it is not used.
? semiconductor MSM7661 15/40 register description registers controlled by i 2 c bus are shown below. a register setting value with an "*" indicates the default. enter "0" to the undefined register when setting registers. mode register a (mra) mra[7] ntsc/pal auto select 0: fix *1: auto mra[6] synchronization mode 0: tv mode *1: vtr mode mra[5] chroma format *0: offset binary 1: 2's complement mra[4] override *0: external terminal mode 1: register mode mra[3] video input mode *0: composite video input 1: s video input mra[2:0] video input mode *000: ntsc ccir601 13.5 mhz 001: ntsc square pixel 12.27 mhz 010: ntsc 4fsc 14.31818 mhz 100: pal ccir601 13.5 mhz 101: pal square pixel 14.75 mhz mode register b (mrb) mrb[7] sub pixel alignment *0: sub pixel alignment is used. 1: sub pixel alignment is not used. mrb[6] color killer mode *0: auto color killer (chrominance signal level becomes "0" when color burst level is below specified value.) *1: forced color killer on (chrominance signal level is forced to be "0".) mrb[5] pixel sampling ratio *0: (4:2:2) 1: (4:1:1) mrb[4] blue back 0: off (v ideo signal is demodulated and output regardless of synchronization detection .) *1: auto (blue back is output when synchro- nization is not detected.)
? semiconductor MSM7661 16/40 mrb[3] sync enable, clamping pulse 0: hsy outputs "high" level. *1: hsy outputs active. mrb[2] data-pass control *0: decimeter is used at 2x sampling. 1: no decimeter is used. (note) this register becomes valid at doube-speed clock input(27 mhz). mrb[1:0] y/c separation mode *00: adaptive comb filter (operation mode is selected monitoring the correlation of 3 lines.) 01: nonadaptive comb filter (operation mode is always fixed.) 10: comb filter is not used. (trap filter is used.) 11: undefined (note) adaptive comb filter: 2/3-line comb filter at ntsc comb filter/trap filter at pal non-adaptive comb filter: 3-line comb filter at ntsc 2-line cosine comb filter at pal horizontal sync trimmer (hsyt) hsyt[7:4] hsy begin trimmer (8/pixel) 0xc: C4 (C32) to 0xb: +11 (+88) hsyt[3:0] hsy stop trimmer (8/pixel) 0xc: C4 (C32) to 0xb: +11 (+88) sync threshold level adjust (sthr) sthr[7:0] sync depth 0x0: C0 to *0x37:55 to 0xff:255 (note) the sync signal detect threshold level is adjusted. horizontal sync delay (hsdl) hsdl[7:0] hsync_l delay trimmer (4/pixel) 0x80: C128 (C512) to 0x7f: +127 (508) horizontal valid trimmer (hvalt) hvalt[7:0] hvalid begin trimmer (1/pixel) 0x8: C8 to 0x7: +7 hvalt[3:0] hvalid stop trimmer (1/pixel) 0x8: C8 to 0x7: +7
? semiconductor MSM7661 17/40 vertical valid trimmer (vvalt) vvalt[7:4] vvalid begin trimmer (1/line) 0x8: C8 to 0x7: +7 vvalt[3:0] vvalid stop trimmer (1/line) 0x8: C8 to 0x7: +7 luminance control (lumc) lumc[7] output level limiter *0: off 1: on (note) the limit range is from 16 to 235 at limiter on. lumc[6] use of pre-filter 0: prefilter is not used. *1: prefilter is used. lumc[5:4] aperture bandpass select *00: middle range 01: 10: 11: high range lumc[3:2] coring range select *00: coring off 01: +/C4lsb 10: +/C5lsb 11: +/C7lsb lumc[1:0] aperture filter weighting factor *00: 0 01: 0.25 10: 0.75 11: 1.5 agc/pedestral loop filter control (agclf) agclf[7:6] agc loop filter time constant 00: slow *01: medium 10: fast 11: fixed agclf[5:0] agc reference level 0x20: C32 to 0x1f: +31
? semiconductor MSM7661 18/40 sync separation level (ssepl) ssepl[7] pedestal clamp on/off *0: pedestal clamp is not used. 1: pedestal clamp is used. (agc will not operate.) ssepl[6:0] sync separation level 0x40: C64 to 0x3f: +63 chrominance control (chrc) chrc[7:4] undefined chrc[7:3] c-output level limiter 0: *off 1: on (note) the limit range is from16 to 224 at limiter on. chrc[2] chroma bandpass filter 0: off *1: on chrc[1:0] color kill threshold factor 00: 0.5 color burst level *01: 0.25 color burst level 10: 0.125 color burst level 11: 0 (color killer off) acc loop filter control (acclf) acclf[7] undefined acclf[6:5] acc loop filter time constant 00: slow *01: medium 10: fast 11: fixed acclf[4:0] acc reference level 0x10: C16 to 0x0f: +15 hue control (hue) hue[7:0] hue control 0x80: C180 degrees to 0x7f: 178.6 degrees
? semiconductor MSM7661 19/40 optional mode register (omr) omr[7:6] undefined omr[5:3] multiplex signal detection level (57ire) (vbid etc.) (63ire) *(68ire) ? ? (97ire) omr[2] hi-z on sleep for out-pin *0: active 1: hi-z omr[1:0] signal indicate mode *00: ntsc/pal 01: sout (multiplex signal detect) 10: hdet (h-sync detect) 11: undefined output phase control for data y (opcy) opcy[7:2] undefined opcy[1:0] output phase control for data y *0: normal 1: forward l clock 2: backward 2 clocks 3: backward l clock output phase control for data c (opcc) opcc[7:2] undefined opcc[1:0] output phase control for data c *0: normal 1: forward l clock 2: backward 2 clocks 3: backward l clock
? semiconductor MSM7661 20/40 functional description input signal level input signal is 8 bits in a straight binary format. the recommended input range is shown below. reserved 255 iuminance 200 sync 60 0 chrominance +dc input black level 13 246 cvbs[7:0] input range
? semiconductor MSM7661 21/40 output format the ycbcr 4:2:2 format and 4:1:1 format are shown below. the output format can be changed by register settings. pixel byte sequence output y7(msb) y6 y5 y4 y3 y2 y1 y0(lsb) y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 c7(msb) c6 c5 c4 c3 c2 c1 c0(lsb) cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 y point 0 2 3 4 5 1 c point 0 2 4 pixel byte sequence output y7(msb) y6 y5 y4 y3 y2 y1 y0(lsb) y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 c7(msb) c6 c5 c4 c3 c2 c1 c0(lsb) cb7 cb6 cr7 cr6 0 0 0 0 cb5 cb4 cr5 cr4 0 0 0 0 y point 0 2 3 4 5 1 c point 0 4 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 67 cb7 cb6 cr7 cr6 0 0 0 0 cb5 cb4 cr5 cr4 0 0 0 0 cb3 cb2 cr3 cr2 0 0 0 0 cb1 cb0 cr1 cr0 0 0 0 0 cb3 cb2 cr3 cr2 0 0 0 0 cb1 cb0 cr1 cr0 0 0 0 0 ycbcr 4:2:2 format ycbcr 4:1:1 format
? semiconductor MSM7661 22/40 timing description a/d converter support signal the timing wave form of hsy/hcl signals, which measure the sync chip and clamp timing for the a/d converter, is as follows. color burst cvbs hsy line control signal the line control signal timing is as follows. y0 y1 y2 y3 y(n) y(n+1) y[7:0] hvalid clko clk cb0 cr0 cb2 cr2 cb(n) cr(n) c[7:0] a/d converter support signal line control timing
? semiconductor MSM7661 23/40 total number of pixels the total number of pixels vary depending on the mode and frequency used, as shown below (default values when typical signals are input). video mode total hblk pixels hsync.back-porch front-porch sampling rate total pixels active pixels video and sampling mode ntsc 138 122 16 13.5 mhz 858 720 140 112 28 12.27 mhz (sq) 780 640 142 134 8 14.32 mhz (4fsc) 910 768 144 130 14 13.5 mhz 864 720 176 142 34 14.75 mhz (sq) 944 768 pal
? semiconductor MSM7661 24/40 vertical synchronizing signal the vertical synchronizing signal timing is as follows. 524525123456789 2122 cvbs hvalid hsync_l vsync_l sync (csync_l) vvalid odd 262 263 264 265 266 267 268 269 270 271 283 284 285 cvbs hvalid hsync_l vsync_l sync (csync_l) vvalid odd vertical synchronizing signal (ntsc 60 hz)
? semiconductor MSM7661 25/40 621622623624625123456 2324 cvbs hvalid hsync_l sync (csync_l) vsync_l vvalid odd 309 310 311 312 313 314 315 316 317 318 336 337 338 cvbs hvalid hsync_l sync (csync_l) vsync_l vvalid odd vertical synchronizing signal (pal 50 hz)
? semiconductor MSM7661 26/40 horizontal synchronizing signal the horizontal synchronizing signal timing is as follows. y[7:0] hvalid hsync_l 60 pixels horizontal timing
? semiconductor MSM7661 27/40 i 2 c bus format the i 2 c-bus interface input format is shown below. as mentioned above, the write operation can be executed from subaddress to subaddress continuously. when the write operation is executed at subaddresses discontinuously, the acknowledge and stop condition formats are input repeatedly after data 0. if one of the following matters occurs, the decoder will not return "a" (acknowledge). ? the slave address does not match. ? a non-existent subaddress is specified. ? the write attribute of a register does not match "x" (read/write control bit). the input timing is shown below. s slave address a subaddress data n description start condition slave address 1000001x, 8th bit is write signal. acknowledge. generated by slave subaddress byte data to write to address designated by subaddress. symbol p stop condition slave address s subaddress a data 0 a a ...... data n a p 12 789 ack 12 3-8 9 ack s start condition p stop condition data line stable: data valid change of data allowed scl sda msb t c_scl i 2 c-bus basic input/output timing
? semiconductor MSM7661 28/40 operation mode setting the video mode includes ; 1. internal terminal mode to be directly set by a dedicated terminal 2. register setting mode to be specified by setting the internal registers these modes can be changed by the mode register mra [4]. the reset state (default) is the external terminal mode. the following registers can be set in the external terminal mode. mra[3] input signal mode *0: composite video input 1: s-video input mra[2 : 0] input mode *000: ntsc itu-r601 13.5 mhz 001: ntsc square pixel 12.27 mhz 010: mtsc 4fsc 14.31818 mhz 100: pal itu-r601 13.5 mhz 101: pal square pixel 14.75 mhz operation clock setting the operation clock settings at itu-r601 are shown below. input clock input data clksel pin register (mrb2) clock for a/d converter 27.0 mhz 27.0 mhz "l" "0" (decimation filter used) clkx2o (27 mhz) 27.0 mhz 13.5 mhz "l" "1" (unused) clkxo (13.5 mhz) 13.5 mhz 13.5 mhz "h" "1" (unused) clkx2o or clkxo (13.5 mhz) when the double speed clock is used, data can be input at a double speed or at an ordinary speed by setting the internal register (mrb2) and the clock for the a/d converter. the internal processing after decimation filter is performed at an ordinary speed.
? semiconductor MSM7661 29/40 internal registers register list d7 mra7 mrb7 hsyt7 d6 d5 d4 data byte d3 d2 d1 d0 subaddress register function mode register a (mra) mode register b (mrb) horizontal sync trimmer (hsyt) sthr7 sync threshold level adjust (sthr) hsdl7 horizontal sync delay (hsdl) hvalid7 horizontal valid trimmer (hvalid) vvalid7 vertical valid trimmer (vvalid) lumc7 luminance control (lumc) agclf7 agc/pedestal loop filter control (agclf) ssepl7 sync separation level (ssepl) chrc7 chrominance control (chrc) acclf7 acc loop filter control (acclf) hue7 hue control (hue) omr7 optional mode register (omr) mra6 mrb6 hsyt6 sthr6 hsdl6 hvalid6 vvalid6 lumc6 agclf6 ssepl6 chrc6 acclf6 hue6 omr6 mra5 mrb5 hsyt5 sthr5 hsdl5 hvalid5 vvalid5 lumc5 agclf5 ssepl5 chrc5 acclf5 hue5 omr5 mra4 mrb4 hsyt4 sthr4 hsdl4 hvalid4 vvalid4 lumc4 agclf4 ssepl4 chrc4 acclf4 hue4 omr4 mra3 mrb3 hsyt3 sthr3 hsdl3 hvalid3 vvalid3 lumc3 agclf3 ssepl3 chrc3 acclf3 hue3 omr3 mra2 mrb2 hsyt2 sthr2 hsdl2 hvalid2 vvalid2 lumc2 agclf2 ssepl2 chrc2 acclf2 hue2 omr2 mra1 mrb1 hsyt1 sthr1 hsdl1 hvalid1 vvalid1 lumc1 agclf1 ssepl1 chrc1 acclf1 hue1 omr1 mra0 mrb0 hsyt0 sthr0 hsdl0 hvalid0 vvalid0 lumc0 agclf0 ssepl0 chrc0 acclf0 hue0 omr0 0 1 2 3 4 5 6 7 8 9 a b c d opcy7 output phase control for data y (opcy) opcy6 opcy5 opcy4 opcy3 opcy2 opcy1 opcy0 e opcc7 output phase control for data c (opcc) opcc6 opcc5 opcc4 opcc3 opcc2 opcc1 opcc0 f
? semiconductor MSM7661 30/40 relationship between register setting value and adjusted value horizontal sync trimmer position adjustment of sync chip clamp timing signal hsyt [7:4] :adjusting the starting position register setting value (ox) adjusted value (pixel) cdef0123456789ab C32 C24 C16 C8 0 +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88 hsyt [3:0] :adjusting the end position cdef0123456789ab C32 C24 C16 C8 0 +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88 register setting value (ox) adjusted value (pixel) horizontal sync delay adjustment of the starting position of horizontal sync signal hsdl [7:0] 89abcdef01234567 msb[7 : 4] C512 C448 C384 C320 C256 C192 0 +64 +128 +192 +256 +320 +384 +448 C508 C444 C380 C316 C252 C188 +4 C504 C440 C376 C312 C248 C184 +8 C500 C436 C372 C308 C244 C180 +12 C496 C432 C368 C304 C240 C176 +16 C492 C428 C364 C300 C236 C172 +20 C488 C424 C360 C296 C232 C168 +24 C484 C420 C356 C292 C228 C164 +28 C480 C416 C352 C288 C224 C160 +32 C476 C412 C348 C284 C220 C156 +36 C472 C408 C344 C280 C216 C152 +40 C468 C404 C340 C276 C212 C148 +44 C464 C400 C336 C272 C208 C144 +48 C460 C396 C332 C268 C204 C140 +52 C456 C392 C328 C264 C200 C136 +56 C452 C388 C324 C260 C196 C132 +60 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C128 C124 C120 C116 C112 C108 C104 C100 C96 C92 C88 C84 C80 C76 C72 C68 C64 C60 C56 C52 C48 C44 C40 C36 C32 C28 C24 C20 C16 C12 C8 C4 +68 +72 +76 +80 +84 +88 +92 +96 +100 +104 +108 +112 +116 +120 +124 +132 +136 +140 +144 +148 +152 +156 +160 +164 +168 +172 +176 +180 +184 +188 +196 +200 +204 +208 +212 +216 +220 +224 +228 +232 +236 +240 +244 +248 +252 +260 +264 +268 +272 +276 +280 +284 +288 +292 +296 +300 +304 +308 +312 +316 +324 +328 +332 +336 +340 +344 +348 +352 +356 +360 +364 +368 +372 +376 +380 +388 +392 +396 +400 +404 +408 +412 +416 +420 +424 +428 +432 +436 +440 +444 +452 +456 +460 +464 +468 +472 +476 +480 +484 +488 +492 +496 +500 +504 +508
? semiconductor MSM7661 31/40 horizontal valid trimmer position adjustment of horizontal valid pixel timing signal hvalt [7:4] :adjusting the starting position 89abcdef01234567 C8 C7 C6 C5 C4 C3 C2 C1 0 +1 +2 +3 +4 +5 +6 +7 register setting value (ox) adjusted value (pixel) hvalt [3:0] :adjusting the end position 89abcdef01234567 C8 C7 C6 C5 C4 C3 C2 C1 0 +1 +2 +3 +4 +5 +6 +7 register setting value (ox) adjusted value (pixel) vertical valid trimmer position adjustment of vertical valid line timing signal vvalt [7:4] :adjusting the starting position vvalt [3:0] :adjusting the end position 89abcdef01234567 C8 C7 C6 C5 C4 C3 C2 C1 0 +1 +2 +3 +4 +5 +6 +7 register setting value (ox) adjusted value (line) 89abcdef01234567 C8 C7 C6 C5 C4 C3 C2 C1 0 +1 +2 +3 +4 +5 +6 +7 register setting value (ox) adjusted value (line) agc loop filter control agclf [5:0] :adjusting sync level 2301 msb [5 : 4] 0 +16 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb register setting value (ox)
? semiconductor MSM7661 32/40 sync separation level ssepl [6:0] :adjusting the blanking level 45670123 msb [6 : 4] C64 C48 0 +16 +32 +48 C63 C47 +1 C62 C46 +2 C61 C45 +3 C60 C44 +4 C59 C43 +5 C58 C42 +6 C57 C41 +7 C56 C40 +8 C55 C39 +9 C54 C38 +10 C53 C37 +11 C52 C36 +12 C51 C35 +13 C50 C34 +14 C49 C33 +15 0 1 2 3 4 5 6 7 8 9 a b c d e f [3 : 0] C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 lsb lsb register setting value (ox) acc loop filter control acclf [4:0] :adjusting the color burst level 10 msb [4] 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb register setting value (ox)
? semiconductor MSM7661 33/40 hue control adjustment of color subcarrier phase hue [7:0] 89abcdef01234567 msb [7 : 4] C180.0 C157.5 C135.0 C112.5 C90.0 C67.5 +0.0 +22.5 +45.0 +67.5 +90.0 +112.5 +135.0 +157.5 C178.6 C156.1 C133.6 C111.1 C88.6 C66.1 +1.4 C177.2 C154.7 C132.2 C109.7 C87.2 C64.7 +2.8 C175.8 C153.3 C130.8 C108.3 C85.8 C63.3 +4.2 C174.4 C151.9 C129.4 C106.9 C84.4 C61.9 +5.6 C173.0 C150.5 C128.0 C105.5 C83.0 C60.5 +7.0 C171.6 C149.1 C126.6 C104.1 C81.6 C59.1 +8.4 C170.2 C147.7 C125.2 C102.7 C80.2 C57.7 +9.8 C168.8 C146.3 C123.8 C101.3 C78.8 C56.3 +11.3 C167.3 C144.8 C122.3 C99.8 C77.3 C54.8 +12.7 C165.9 C143.4 C120.9 C98.4 C75.9 C53.4 +14.1 C164.5 C142.0 C119.5 C97.0 C74.5 C52.0 +15.5 C163.1 C140.6 C118.1 C95.6 C73.1 C50.6 +16.9 C161.7. C139.2 C116.7 C94.2 C71.7 C49.2 +18.3 C160.3 C137.8 C115.3 C92.8 C70.3 C47.8 +19.7 C158.9 C136.4 C113.9 C91.4 C68.9 C46.4 +21.1 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb [3 : 0] C45.0 C43.6 C42.2 C40.8 C39.4 C38.0 C36.6 C35.2 C33.8 C32.3 C30.9 C29.5 C28.1 C26.7 C25.3 C23.9 C22.5 C21.1 C19.7 C18.3 C16.9 C15.5 C14.1 C12.7 C11.3 C9.8 C8.4 C7.0 C5.6 C4.2 C2.8 C1.4 +23.9 +25.3 +26.7 +28.1 +29.5 +30.9 +32.3 +33.8 +35.2 +36.6 +38.0 +39.4 +40.8 +42.2 +43.6 +46.4 +47.8 +49.2 +50.6 +52.0 +53.4 +54.8 +56.3 +57.7 +59.1 +60.5 +61.9 +63.3 +64.7 +66.1 +68.9 +70.3 +71.7 +73.1 +74.5 +75.9 +77.3 +78.8 +80.2 +81.6 +83.0 +84.4 +85.8 +87.2 +88.6 +91.4 +92.8 +94.2 +95.6 +97.0 +98.4 +99.8 +101.3 +102.7 +104.1 +105.5 +106.9 +108.3 +109.7 +111.1 +113.9 +115.3 +116.7 +118.1 +119.5 +120.9 +122.3 +123.8 +125.2 +126.6 +128.0 +129.4 +130.8 +132.2 +133.6 +136.4 +137.8 +139.2 +140.6 +142.0 +143.4 +144.8 +146.3 +147.7 +149.1 +150.5 +151.9 +153.3 +154.7 +156.1 +158.9 +160.3 +161.7 +163.1 +164.5 +165.9 +167.3 +168.8 +170.2 +171.6 +173.0 +174.4 +175.8 +177.2 +178.6 register setting value (ox)
? semiconductor MSM7661 34/40 filter characteristics 0 C20 C40 C60 C80 C100 0123 frequency [mhz] band pass filter (ntsc itu-r601) level [db] 456 0 C20 C40 C60 C80 C100 0123 frequency [mhz] band pass filter (pal itu-r601) level [db] 456
? semiconductor MSM7661 35/40 0 C20 C40 C60 C80 C100 0123 frequency [mhz] trap filter (ntsc itu-r601) level [db] 456 0 C20 C40 C60 C80 C100 0123 frequency [mhz] trap filter (pal itu-r601) level [db] 456
? semiconductor MSM7661 36/40 0 C20 C40 C60 C80 C100 0123 frequency [mhz] pre filter level [db] 456 0 C20 C40 C60 C80 C100 0123 frequency [mhz] sharp filter level [db] 456
? semiconductor MSM7661 37/40 0 C20 C40 C60 C80 C100 0246 frequency [mhz] level [db] 81012 decimation filter * the characteristics of the various filters shown above are based on design data.
? semiconductor MSM7661 38/40 basic application circuit example application 1 mode setting video signal: ntsc-composite clkx2: 27 mhz MSM7661 hsy i 2 c controller sda scl reset_l test2 (sleep) v dd y0...y7 gnd clksel pllsel mode0 mode1 mode2 mode3 vsync_l hsync_l syssel clkxo odd vvalid hvalid vc0_cp clkx2 osc a/d c: cxd1179q (sony) lpf1: 628ljn-1471 (toko) l l l dip sw frame memory or image lsi l sync clkxo2 cvbs0 cvbs7 cd0 cd7 8 3.3 v 3.3 v 8 c0...c7 8 8 a/d c input circuit video in lpf1
? semiconductor MSM7661 39/40 application 2 mode setting video signal: ntsc-composite clkx2: 13.5 mhz MSM7661 hsy i 2 c controller sda scl reset_l test2 (sleep) v dd y0...y7 gnd clksel pllsel mode0 mode1 mode2 mode3 vsync_l hsync_l syssel clkxo odd vvalid hvalid vc0_cp clkx2 osc a/d c: upc659 (nec) lpf1: 628ljn-1471 (toko) l l l dip sw frame memory or image lsi l sync clkxo2 cvbs0 cvbs7 cd0 cd7 8 3.3 v 3.3 v 8 c0...c7 8 8 a/d c input circuit video in lpf1
? semiconductor MSM7661 40/40 package outlines and dimensions (unit : mm) 64-pin plastic qfp

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